The present application relates to semiconductor structures and methods of forming the same. More particularly, the present application relates to semiconductor structures including a stack of, from bottom to top, a metal semiconductor alloy portion and a transition metal-metal semiconductor alloy portion located on each side of a functional gate structure. The present application also provides methods for forming such semiconductor structures.
Field effect transistors (FETs) are the basic building block of today's integrated circuits. Such transistors can be formed in conventional bulk substrates (such as silicon) or in semiconductor-on-insulator (SOI) substrates.
State of the art FETs can be fabricated by depositing a gate conductor over a gate dielectric and a semiconductor substrate. Generally, the FET fabrication process implements lithography and etching processes to define the gate structures. After providing the gate structures, source/drain extensions are formed into a portion of the semiconductor substrate and on both sides of each gate structure by ion implantation. Sometimes this implant is performed using a spacer to create a specific distance between the gate structure and the implanted junction. In some instances, such as in the manufacture of an n-FET device, the source/drain extensions for the n-FET device are implanted with no spacer. For a p-FET device, the source/drain extensions are typically implanted with a spacer present. A thicker spacer is typically formed after the source/drain extensions have been implanted. In some instances, deep source/drain implants can be performed with the thick spacer present. In other instances, and for advanced technologies, the source region and the drain region can be formed using a selective epitaxial growth process. High temperature anneals can be performed to activate the junctions after which the source/drain and top portion of the gate are generally converted into a metal semiconductor alloy (i.e., a metal silicide). The formation of the metal semiconductor alloy typically requires that a transition metal be deposited on the semiconductor substrate followed by a process to produce the metal semiconductor alloy. Such a process forms low resistivity metal semiconductor alloy contacts to the deep source/drain regions.
In current technologies, and among other limiting factors, the metal semiconductor alloy containing contacts can be affected by the following two defects: (1) Encroachment of the metal semiconductor alloy which typically increases leakage through the source/drain junction and can also completely short the source region and the drain region of the device. (2) Spotty (non-uniform) metal semiconductor alloys which may cause unwanted etching of the metal semiconductor alloy contact during a subsequently performed etch.
These two defects are either formed during a subsequently performed etching process or the defects are enhanced by a subsequently performed etching process. Limiting these effects is critical for upcoming technologies.